INTEND OF LUT/MUX COMPLEXS BY USING FPGA MODUS OPERANDI

B Lingam, K Sree Vidya

Abstract


For reducing the area and improving the performance of logical circuits, a combination of Lookup Table (LUT) with multiplexer methodology is applied together. By implementing this kind of architecture a new MUX: LUT structure is designed, which works based on the number of comparators and logical circuits. This implementation is more suitable for both accounting for complex logic block and routing area while maintaining mapping depth. Interconnections are increasingly the dominant contributor to delay, area and energy consumption in Complementary Metal-Oxide Semiconductor (CMOS) digital circuits. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We have to use the 512bit quaternary Lookup Table for a high level of operations in the FPGA. The proposed architecture of this paper will be planned to implemented and also analysis the output current, output voltage, area using Xilinx 14.3.


Keywords


LUT; MUX; CMOS; FPGA; Xlinx; Limitations; mode cells;

References


I. Kuon and J. Rose, “Measuring the distance in the seam FPGAs and ASICs,” in Proceedings of one's 2006 ACM/SIGDA 14th foreign panel discussion on Field programmable doorway arrays. ACM New York, NY, USA, 2006, pp. 21–30.

K. Wu and Y. Tsai, “Structured ASIC, Evolution or Revolution,” April 2004, pp. 103–106.

T. Okamoto, T. Kimoto, and N. Maeda, “Design Methodology and Tools for NEC Electronics Structured ASIC,” April 2004, pp. 90–96.

J. Pistorius, M. Hutton, J. Schleicher, M. Iotov, E. Julias, and K. Tharmalignam, “Equivalence Verification of FPGA and Structured ASIC Implementations,” August 2007, pp. 423–428.

H. Parvez, Z. Marrakchi, and H. Mehrez, “ASIF: Application Specific Inflexible FPGA,” in International Conference on Field Programmable Technology, 2009. FPT 2009, 2009, pp. 112–119.

V. Betz and J. Rose, “VPR: A New Packing Placement and Routing Tool for FPGA consult,” International Workshop on FPGA, pp. 213– 22, 1997


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