DESIGN AND IMPLEMENTATION OF CONVOLUTIONAL ENCODER AND VITERBI DECODER WITH VARIABLE CODE RATE

Sivakalyan Mahanthi, K.B.S.D. Sarma

Abstract


It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolution encoding with Viterbi decoding is a good forward error correction technique suitable for channels affected by noise degradation. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. A new efficient fangled Viterbi algorithm is proposed in this paper with less complexity and processing time along with 2 bit error correction capabilities and variable code rate. The design is successfully simulated using Xilinx ISIM and targeted to xc3s500e FPGA device.


Keywords


Convolutional Encoder; Viterbi Decoder; Verilog HDL; FPGA; PNPH unit;

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